用状态机?/p>
ADC0809
的采样控制电路实?/p>
1
、实验目的:学习用状态机?/p>
A/D
转换?/p>
ADC0809
的采样控制电路的实现?/p>
2
、实验原理:
ADC0809
?/p>
CMOS
?/p>
8
?/p>
A/D
转换器,片内?/p>
8
路模拟开关,可控?/p>
8
?/p>
模拟量中的一个进入转换器中?/p>
ADC0809
的分辨率?/p>
8
位,转换时间?/p>
100us
,含锁存控制
?/p>
8
路多路开关,输出有三态缓冲器控制,单
5V
电源供电?/p>
主要控制信号说明:如?/p>
6-28
所示,
START
是转换启动信号,高电平有效;
ALE
?/p>
3
位通道选择地址?/p>
ADDC
?/p>
ADDB
?/p>
ADDA
)信号的锁存信号。当模拟量送至某一输入端(?/p>
IN1
?/p>
IN2
等)
,由
3
位地址信号选择,而地址信号?/p>
ALE
锁存?/p>
EOC
是转换情况状态信号(?/p>
似于
AD574
?/p>
STATUS
?/p>
,当启动转换?/p>
100us
后,
EOC
产生一个负脉冲,以示转换结束;?/p>
EOC
的上升沿后,若使输出使能信号
OE
为高电平,则控制打开三态缓冲器,把转换好的
8
位数据结果输至数据总线。至?/p>
ADC0809
的一次转换结束了?/p>
【例
6-28
?/p>
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADCINT IS
PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --0809
?/p>
8
位转换数据输?/p>
CLK ,EOC : IN STD_LOGIC; --CLK
是转换工作时?/p>
LOCK1, ALE, START, OE, ADDA : OUT STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END ADCINT;
ARCHITECTURE behav OF ADCINT IS
TYPE states IS (st0, st1, st2, st3,st4,st5,st6) ; --
定义各状态子类型
SIGNAL current_state, next_state: states :=st0 ;
SIGNAL REGL
: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK
: STD_LOGIC; --
转换后数据输出锁存时钟信?/p>
BEGIN
ADDA <= '1'; LOCK1 <=LOCK;
PRO: PROCESS(current_state,EOC) BEGIN --
规定各状态转换方?/p>
CASE current_state IS
WHEN st0 => ALE<='0';START<='0';OE<='0';LOCK<='0' ;next_state <= st1;
WHEN st1 => ALE<='1';START<='0';OE<='0';LOCK<='0' ;next_state <= st2;
WHEN st2 => ALE<='0';START<='1';OE<='0';LOCK<='0' ;next_state <= st3;
WHEN st3 => ALE<='0';START<='0';OE<='0';LOCK<='0';
IF (EOC='1') THEN next_state <= st3; --
测试
EOC
的下降沿
ELSE next_state <= st4;
END IF ;
WHEN st4=> ALE<='0';START<='0';OE<='0';LOCK<='0';
IF (EOC='0') THEN next_state <= st4; --
测试
EOC
的上升沿?/p>
=1
表明转换结束
ELSE next_state <= st5; --
继续等待
END IF ;
WHEN st5=> ALE<='0';START<='0';OE<='1';LOCK<='0';next_state <= st6;
WHEN st6=> ALE<='0';START<='0';OE<='1';LOCK<='1';next_state <= st0;
WHEN OTHERS => ALE<='0';START<='0';OE<='0';LOCK<='0';next_state <= st0;