ALTERA SERDES IP瀹炰緥搴旂敤 - 鐧惧害鏂囧簱

棣栭〉

搴撳簱AI

骞垮満

鍘嗗彶

鏀惰棌

浜戠洏

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ALTERA SERDES IP

瀹炰緥搴旂敤

 

 

涓轰簡鐔熸倝

ALTERA

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SERDES IP

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璇曠潃鐢熸垚

ALT_LVDS_RX

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ALT_LVDS_TX

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IP

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鐪熸祴璇曘�?/p>

骞冲彴锛?/p>

QUARTUS 10.1 +Moelsim6.6SE 

 

FPGA:Stratix IV 820 

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Stratix 

IV 820

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LVDS

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LVDS

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浣庡姛鑰楅�氱敤鐨?/p>

I/O

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Stratix IV FPGA

瑕佹眰

2.5V Vccio

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LVDS

瑕佹眰杈撳叆

buffer

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2

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100

惟

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Stratix IV FPGA

浣?/p>

鐢?/p>

OCT(on-chip 

differential 

termination)

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100

惟

宸�鍒嗙粓绔�鐢甸樆銆備絾

鏄�杩欎簺鐗囦笂鍙�閫夌殑

100

惟

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Stratix 

IV 

FPGA

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row 

banks

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6-31

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